Image format
firmware_v5.0.3.bin is a standard ESP-IDF application image (esp_image_header_t),
not a raw binary. By the ESP-IDF format it begins with the magic byte 0xE9 and is loaded
by the second-stage bootloader into the OTA app partition.
Every header field above is read directly from the image file with
esptool image-info
(magic 0xE9, 7 segments, entry 0x40081144, DIO / 4 MB / 40 MHz, chip_id 0). The
independent re-analysis from the carved segments corroborates the segment count, entry
point, and the esp_app_desc_t at 0x20; the SPI/flash bytes also match the
ESP32_GENERIC-OTA board default.Build metadata (esp_app_desc_t)
The application descriptor sits at the start of the first mapped segment.
v5.4-dirty means the ESP-IDF tree had uncommitted local changes when the image was
built. This is normal for vendor firmware and does not indicate tampering.Integrity
The image carries two integrity mechanisms, both validated withesptool:
- A one-byte XOR checksum over the segment data:
0xb2(valid). - An appended SHA-256 (
hash_appendedset):a6c392bf…3e622dcd(valid), which the bootloader verifies before boot. This is an image-integrity hash, not a cryptographic signature; no Secure Boot signature block was observed in this image.
These three hashes are distinct: the image-file SHA-256 (
bfe1f5a4…, the whole .bin,
listed by the release API), the appended validation hash (a6c392bf…, inside the image),
and the app ELF hash (97a29359…, in esp_app_desc_t, pinning the source ELF).
For v5.0.2 they were a6d05597…, 2a01e0f5… and 311224….Runtime: MicroPython
The native Xtensa code in the image is almost entirely the MicroPython v1.25.0 interpreter plus ESP-IDF components (WiFi, NimBLE Bluetooth, mbedTLS, FreeRTOS, LittleFS/VFS). Totem’s application is written in Python and frozen into the image.webrepl.py, upysh.py, and mip (the MicroPython package installer)
in the frozen set indicates a developer-oriented build lineage, though whether WebREPL
is enabled at runtime depends on boot configuration held in bytecode/NVS.
See architecture for the module breakdown and
memory map for the segment layout.